1. Field of the Invention
The present invention relates to a data processing apparatus and method for testing a circuit block using scan chains.
2. Description of the Prior Art
Scan chains are a well-known method for testing a circuit structurally. They allow data to be scanned in and out of a circuit during a test mode of operation in an attempt to detect manufacturing defects.
Scan chains are typically inserted into a circuit design during an Electronic Design Automation (EDA) process. For example, a Hardware Description Language (HDL) description of a circuit (one example of an HDL being Verilog) may be input to an EDA tool developed by a particular EDA vendor, with the EDA tool generating from the HDL description a circuit design (often also referred to as a macrocell). During this process, the EDA tool will typically insert a number of scan chains to allow test data to be input to particular portions of the circuit during a test mode of operation, and following application of that test data to the circuit portion; to then enable output test data to be captured and output from the circuit.
In modern data processing systems, the number of scan chains required to thoroughly test a circuit is becoming very large, but the scan-in and scan-out interfaces provided within the circuit are typically constrained in their size and accordingly will only provide a certain number of pins for scanning in and scanning out the required test data.
In recent years, different EDA vendors have provided support in their tools to allow compressed input test data to be input through the scan-in interface, and similarly for compressed output test data to be output from the scan-out interface. Such support usually involves the inclusion of some hardware in the circuit for decompression of compressed input test data prior to routing of the decompressed test data to the scan chains, and similarly some hardware for receiving the outputs from the scan chains and compressing those outputs in order to generate compressed output test data to route from the scan-out interface.
FIG. 1 schematically illustrates such an approach. In FIG. 1, the scan-in (SI) pins 10 and the scan-out (SO) pins 50 are connected to logic 20, 40 inserted by the EDA tool. These in turn connect to a plurality of internal scan chains 30. The EDA tool typically implements many more internal scan chains than there are scan-in and scan-out pins. Compressed data is hence scanned in on m SI pins, decompressed by logic 20, and then routed through n internal scan chains, where n is greater than m.
An analogous process occurs in reverse with the n outputs of the internal scan chains being routed via the compression logic 40 to the m scan-out pins.
A number of EDA tools use this principle. However, the logic used to decompress and compress the data is EDA tool dependent.
It is common to integrate a circuit produced by a particular EDA tool (and hence for example including the scan chains 30 and associated decompression and compression blocks 20, 40) into a larger design, for example a chip including a plurality of different circuit blocks. For example, such internal scan chains and associated decompression and compression blocks 20, 40 may be provided in association with a single processor core, which may be integrated into a high performance multi-processor chip. However, a problem that can arise when such designs are integrated into larger systems is that if one component implements a scan compression scheme from a single EDA vendor, it becomes necessary to use the same EDA vendor's scan compression scheme for the entire chip. This is undesirable when the chip implementer wishes to use a different EDA tool and associated compression scheme in the design of the chip.
To date, EDA vendors have tended to treat their compression and decompression schemes as proprietary, since a scheme that gives a particularly good compression rate can allow a particular EDA vendor to gain a market edge for its EDA tools when compared with the tools of another EDA vendor.
One approach which has been developed with the aim of allowing more interoperability between different EDA tools is set out in the IEEE Standard IEEE 1450.6.1 (via the Accellera organisation, where it is known as the Open Compression Interface (OCI). The Open Compression Interface specifies a language for describing the logic inserted into a design for the purposes of scan compression, for example the decompression block 20 and the compression block 40 of FIG. 1. In theory, this would allow a description of the decompression logic and compression logic inserted into a circuit design by vendor A's EDA tool to be an input to vendor B's EDA tool to enable vendor B's EDA tool to generate test patterns for inserting into that circuit. However, in practice this does still not give a truly vendor neutral solution as EDA tools are generally not capable of utilising another vendor's compression scheme. Further, even if a standardised definition of the decompression and compression logic inserted by a particular vendor into a circuit design can be realised using the Open Compression Interface, there is still the problem that if that design is inserted into a larger chip, it is preferable for the entire chip to use the same EDA vendor's scan compression scheme.